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Espressif Systems /ESP32-S3 /SPI1 /MISC

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Interpret as MISC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CS0_DIS)CS0_DIS 0 (CS1_DIS)CS1_DIS 0 (CK_IDLE_EDGE)CK_IDLE_EDGE 0 (CS_KEEP_ACTIVE)CS_KEEP_ACTIVE 0 (AUTO_PER)AUTO_PER

Description

SPI1 misc register.

Fields

CS0_DIS

Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts.
CS1_DIS

Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts.
CK_IDLE_EDGE

1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle.
CS_KEEP_ACTIVE

SPI_CS line keep low when the bit is set.
AUTO_PER

Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data